********************************************************************************* * * File P5DRIV.ASM completly analysed and commented * * By : Henk van Winkoop (henk@arexx.com) * * Date: 08-08-2004 * ********************************************************************************* * comment between [] is original Conrad comment * *================================================================================ The real p5driv.s19 S1130101190116A5811B0118A581180117A5811ACA S11301110119A581ADF920E8ADF020E9ADE720E0B2 S1130121ADED20E6A604B7A3AD29B6A5A4F8BAA1FE S1130131B7A581A608BE0B2004A607BE0ABFA1B7B6 S1130141A220063FA2B6A5B7A1B6A14939A2493951 S1130151A23FA39BAD54AD38AE0C5A26FDB6A3CD38 S1130161017FB6A2CD017FB6A1CD017F1105130593 S1130171CD0198B7A2CD0198B7A1AD149A815F13AF S1130181014411012402100112015CA30826F0812B S1130191130112051005815F0201FD440301FD01F4 S11301A10102AA805CA30826EF81ADE41201AE0A24 S11301B15A26FD1305AE0A0201055A26FA20EB025E S11301C101FD81A60CB70C81AE0839A411012402EA S11301D11001150114015A26F139A41601170181E0 S11301E1AD1214A41CA520E0AD0A12A41AA520D8AE S11001F1AD0220D415A413A41DA51BA581E7 S9030000FC *================================================================================ p5driv.s19 somewhat expanded S1 13 0101 19 01 16 A5 81 1B 01 18 A5 81 18 01 17 A5 81 1A CA S1 13 0111 01 19 A5 81 AD F9 20 E8 AD F0 20 E9 AD E7 20 E0 B2 S1 13 0121 AD ED 20 E6 A6 04 B7 A3 AD 29 B6 A5 A4 F8 BA A1 FE S1 13 0131 B7 A5 81 A6 08 BE 0B 20 04 A6 07 BE 0A BF A1 B7 B6 S1 13 0141 A2 20 06 3F A2 B6 A5 B7 A1 B6 A1 49 39 A2 49 39 51 S1 13 0151 A2 3F A3 9B AD 54 AD 38 AE 0C 5A 26 FD B6 A3 CD 38 S1 13 0161 01 7F B6 A2 CD 01 7F B6 A1 CD 01 7F 11 05 13 05 93 S1 13 0171 CD 01 98 B7 A2 CD 01 98 B7 A1 AD 14 9A 81 5F 13 AF S1 13 0181 01 44 11 01 24 02 10 01 12 01 5C A3 08 26 F0 81 2B S1 13 0191 13 01 12 05 10 05 81 5F 02 01 FD 44 03 01 FD 01 F4 S1 13 01A1 01 02 AA 80 5C A3 08 26 EF 81 AD E4 12 01 AE 0A 24 S1 13 01B1 5A 26 FD 13 05 AE 0A 02 01 05 5A 26 FA 20 EB 02 5E S1 13 01C1 01 FD 81 A6 0C B7 0C 81 AE 08 39 A4 11 01 24 02 EA S1 13 01D1 10 01 15 01 14 01 5A 26 F1 39 A4 16 01 17 01 81 E0 S1 13 01E1 AD 12 14 A4 1C A5 20 E0 AD 0A 12 A4 1A A5 20 D8 AE S1 10 01F1 AD 02 20 D4 15 A4 13 A4 1D A5 1B A5 81 E7 S9 03 0000 FC |<--------------real-data--------------------->| *================================================================================ p5driv.s19 only addresses and data |--| addresses |<---------------data------------------------->| 0101 19 01 16 A5 81 1B 01 18 A5 81 18 01 17 A5 81 1A 0111 01 19 A5 81 AD F9 20 E8 AD F0 20 E9 AD E7 20 E0 0121 AD ED 20 E6 A6 04 B7 A3 AD 29 B6 A5 A4 F8 BA A1 0131 B7 A5 81 A6 08 BE 0B 20 04 A6 07 BE 0A BF A1 B7 0141 A2 20 06 3F A2 B6 A5 B7 A1 B6 A1 49 39 A2 49 39 0151 A2 3F A3 9B AD 54 AD 38 AE 0C 5A 26 FD B6 A3 CD 0161 01 7F B6 A2 CD 01 7F B6 A1 CD 01 7F 11 05 13 05 0171 CD 01 98 B7 A2 CD 01 98 B7 A1 AD 14 9A 81 5F 13 0181 01 44 11 01 24 02 10 01 12 01 5C A3 08 26 F0 81 0191 13 01 12 05 10 05 81 5F 02 01 FD 44 03 01 FD 01 01A1 01 02 AA 80 5C A3 08 26 EF 81 AD E4 12 01 AE 0A 01B1 5A 26 FD 13 05 AE 0A 02 01 05 5A 26 FA 20 EB 02 01C1 01 FD 81 A6 0C B7 0C 81 AE 08 39 A4 11 01 24 02 01D1 10 01 15 01 14 01 5A 26 F1 39 A4 16 01 17 01 81 01E1 AD 12 14 A4 1C A5 20 E0 AD 0A 12 A4 1A A5 20 D8 01F1 AD 02 20 D4 15 A4 13 A4 1D A5 1B A5 81 *================================================================================ *================================================================================ *=================== CONRAD 'DIE HARD' COMMENT ================================== *================================================================================ ********************************************* *** CCRP5 C-CONTROL DRIVER (by DIE HARD) *** ********************************************* * - IR INTERFACE Byte 1-3 ***** * - PLM RATE OVERRIDE ***** * - EXTPORT DRIVER Byte 1 ***** ********************************************* * - EXTENDED VERSION, LCD DELETED * - PA0 = COMMON DATA * - PA1 = COMM INTERFACE CLOCK * - PA2 = EXTPORT/LCD CLOCK * - PA3 = EXTPORT STROBE * - PA5 = REVERSE LEFT (0=REVERSE) * - PA4 = REVERSE RIGHT (0=REVERSE) ********************************************* *------------ TIMING ----------------------- * EXTPORT WRITE: 115us * * BASIC BYTES 1 AND 2 ARE OCCUPIED * TRANSMIT ENTRY IS * PORT B IST BASIC PORT 1-8 * PROGRAM USES LABEL "A" *================================================================================ *-------------------------------------------------------------------------------- * DEFINE 'EQUATIONS' FOR MICROCONTROLLER REGISTERS *-------------------------------------------------------------------------------- *----- SYSTEM I/O ------- PADDR EQU $0005 ;Data Direction Register port B (DDRB) (not port A!) PADAT EQU $0001 ;data register PORT B (PORTB) (not port A!) PLMA EQU $000A ;Pulse Length Modulation A (PLMA) (pin 20) (left engine speed) PLMB EQU $000B ;Pulse Length Modulation B (PLMB) (pin 21) (right engine speed) MISC EQU $000C ;MISCellaneous register (MISC) *-------------------------------------------------------------------------------- * DEFINE 'EQUATIONS' FOR USER RAM MEMORY LOCATIONS *-------------------------------------------------------------------------------- *----- COMM INTERFACE MEMORY ----- BUFFL EQU $00A1 ;BUFFL is other name for LBYTE (used with Basic) BUFFH EQU $00A2 ;BUFFH is other name for HBYTE (used with Basic) SUBCMD EQU $00A3 ;SUBCMD (used with Basic) *--- EXTPORT INTERFACE MEMORY ---- EXTP EQU $00A4 ;EXTPORT (used with Basic) *---- SYSTEM STATUS ---------- SYSSTAT EQU $00A5 ;SYSSTAT is other name for SYSTEM_STATUS (used with Basic) *-------------------------------------------------------------------------------- * ASSUME THAT FIRST INSTRUCTION IS PLACED AT ADRESS HEX 0x0101 *-------------------------------------------------------------------------------- .org $0101 *================================================================================ * *address * opcode * label * assembler * comment *================================================================================ *####################################### *### define REVR &H0101 ### *####################################### *-------------------------------------------------------------------------------- * REVERSE RIGHT (SET RIGHT ENGINE DIRECTION TO REVERSE) *-------------------------------------------------------------------------------- 0101 19 01 REVR: BCLR 4,PADAT ;clr bit 4 in Port B (PORT5, PB4) = set right engine to reverse 0103 16 A5 BSET 3,SYSSTAT ;set bit 3 in SYSTEM_STATUS (FWD_R) (undocumented) 0105 81 RTS ;return *####################################### *### define REVL &H0106 ### *####################################### *-------------------------------------------------------------------------------- * REVERSE LEFT (SET LEFT ENGINE DIRECTION TO REVERSE) *-------------------------------------------------------------------------------- 0106 1B 01 REVL: BCLR 5,PADAT ;clr bit 5 Port B (PORT6, PB5) = set left engine to reverse 0108 18 A5 BSET 4,SYSSTAT ;set bit 4 in SYSTEM_STATUS (FWD_L) (undocumented) 010A 81 RTS ;return *####################################### *### define FWDR &H010B ### *####################################### *-------------------------------------------------------------------------------- * FORWARD RIGHT (SET RIGHT ENGINE DIRECTION TO FORWARD) *-------------------------------------------------------------------------------- 010B 18 01 FWDR: BSET 4,PADAT ;set bit 4 Port B (PORT5,PB4) = set right engine to forward 010D 17 A5 BCLR 3,SYSSTAT ;clr bit 3 in SYSTEM_STATUS (FWD_R) (undocumented) 010F 81 RTS ;return *####################################### *### define FWDL &H0110 ### *####################################### *-------------------------------------------------------------------------------- * FORWARD LEFT (SET LEFT ENGINE DIRECTION TO FORWARD) *-------------------------------------------------------------------------------- 0110 1A 01 FWDL: BSET 5,PADAT ;set bit 5 Port B (PORT6,PB5) = set left engine to forward 0112 19 A5 BCLR 4,SYSSTAT ;clr bit 4 in SYSTEM_STATUS (FWD_L) (undocumented) 0114 81 RTS ;return *####################################### *### define ROTR &H0115 ### *####################################### *-------------------------------------------------------------------------------- * ROTATE RIGHT (SET LEFT ENGINE TO FORWARD AND SET RIGHT ENGINE TO REVERSE) *-------------------------------------------------------------------------------- 0115 AD F9 ROTR: BSR FWDL ;gosub FWDL, set left engine forward 0117 2O E8 BRA REVR ;goto REVR, set right engine reverse *####################################### *### define ROTL &H0119 ### *####################################### *-------------------------------------------------------------------------------- * ROTATE LEFT (SET RIGHT ENGINE TO FORWARD AND SET LEFT ENGINE TO REVERSE) *-------------------------------------------------------------------------------- 0119 AD F0 ROTL: BSR FWDR ;gosub FWDR, set right engine forward 011B 20 E9 BRA REVL ;goto REVR, set left engine reverse *####################################### *### define REV &H011D ### *####################################### *-------------------------------------------------------------------------------- * MOVE REVERSE (SET LEFT ENGINE TO REVERSE AND SET RIGHT ENGINE TO REVERSE) *-------------------------------------------------------------------------------- 011D AD E7 REV: BSR REVL ;gosub REVL, set left engine reverse 011F 20 E0 BRA REVR ;goto REVR, set right engine reverse *####################################### *### define FWD &H0121 ### *####################################### *-------------------------------------------------------------------------------- * MOVE FORWARD (SET LEFT ENGINE TO FORWARD AND SET RIGHT ENGINE TO FORWARD) *-------------------------------------------------------------------------------- 0121 AD ED FWD: BSR FWDL ;gosub FWDL, set left engine forward 0123 20 E6 BRA FWDR ;goto FWDR, set right engine forward *####################################### *### define COMNAV_STATUS &H0125 ### *####################################### *-------------------------------------------------------------------------------- * (CNSTAT) SEND SUBCMD(4)/HBYTE/LBYTE TO CO-PROCESOR, RECEIVE HBYTE/LBYTE... * ...REMOVE SYSTEM_STATUS BITS 0-2 AND COPY SET HBYTE BITS INTO SYSTEM_STATUS *-------------------------------------------------------------------------------- 0125 A6 04 CNSTAT: LDA #$04 ;0x04 in accumulator 0127 B7 A3 STA SUBCMD ;store 0x04 in SUBCMD 0129 AD 29 BSR XX ;gosub XX, send SUBCMD/HBYTE/LBYTE to co-processor, receive HBYTE/LBYTE 012B B6 A5 LDA SYSSTAT ;get SYSTEM_STATUS 012D A4 F8 AND #$F8 ;clear IR/ACR flag bits [CLEAR BITS] 012F BA A1 ORA BUFFL ;copy all bits set in HBYTE, into accu (=SYSTEM_STATUS), ...???... 0131 B7 A5 STA SYSSTAT ;put accu into SYSTEM_STATUS 0133 81 RTS ;return ********************************************************************************* * ACCU X-REGISTER * +---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+ * | . | . | . | . | a | . | . | . | | b | . | . | . | . | . | . | c | * +---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+ * | | * V V * HBYTE LBYTE * +---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+ * | . | . | . | . | a | . | . | . | | b | . | . | . | . | . | . | c | * +---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+ * / / / * / / / * / / / * +---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+ * | . | . | a | . | . | . | b | . | | . | . | . | . | . | c | . | . | Shift HBYTE/LBYTE 2x left * +---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+ * * |-------|---4-bit-channel---|-------8-bit-data---------------| Modified RC5 IR-Data-Frame * * Modified HBYTE and LBYTE are send to co-processor * ********************************************************************************* *####################################### *### define SEND_SPEEDR &H0134 ### *####################################### *-------------------------------------------------------------------------------- * (TXPLMB) TRANSMIT RIGHT ENGINE SPEED BY INFRARED TRANSMITTER *-------------------------------------------------------------------------------- *---(TXPLMB)---prepair-right-engine-speed-to-be-transmitted-by-infrared-transmitter--- 0134 A6 08 TXPLMB: LDA #8 ;store code/channel for Right-Engine Pulse-Length-Modulation (8) in accu 0136 BE 0B LDX PLMB ;copy right engine speed in X-register 0138 20 04 BRA TXX ;prepair and send data by infrared tranmitter *####################################### *### define SEND_SPEEDL &H013A ### *####################################### *-------------------------------------------------------------------------------- * (TXPLMA) TRANSMIT LEFT ENGINE SPEED BY INFRARED TRANSMITTER *-------------------------------------------------------------------------------- *---(TXPLMB)---prepair-left-engine-speed-to-be-transmitted-by-infrared-transmitter--- 013A A6 07 TXPLMA: LDA #7 ;store code/channel for Left-Engine Pulse-Length-Modulation (7) in accu 013C BE 0A LDX PLMA ;copy left engine speed in X-register 013E BF A1 TXX: STX BUFFL ;copy X-register into LBYTE *---copy-accu-and-x-register-into-hbyte-and-lbyte--- 0140 B7 A2 STA BUFFH ;copy accu into HBYTE 0142 20 06 BRA SENDTLM ;send enginespeed by IR-transmitter *####################################### *### define SEND_SYSSTAT &H0144 ### *####################################### *---------- SYSTEM STATUS ------------------ 0144 3F A2 TXSTAT:CLR BUFFH ;clear HBYTE, to make code/channel 0 (0 = sending SYSTEM_STATUS) 0146 B6 A5 LDA SYSSTAT ;get SYSTEM_STATUS 0148 B7 A1 STA BUFFL ;store SYSTEM_STATUS into LBYTE (LBYTE used by SENDTLM) *####################################### *### define SEND_TLM &H014A ### *####################################### *---------- SEND TLM ---------- 014A B6 A1 SENDTLM:LDA BUFFL ;get LBYTE, which holds the transmit data byte [FORMAT] 014C 49 ROL A ;rotate left LBYTE, b7 shifts into carry 014D 39 A2 ROL BUFFH ;rotate left HBYTE, carry shifts into b0 014F 49 ROL A ;rotate left LBYTE, b7 shifts into carry 0150 39 A2 ROL BUFFH ;rotate left HBYTE, carry shifts into b0 0152 3F A3 CLR SUBCMD ;clear SUBCMD, = send Infrared data [->SEND] *####################################### *### define COMNAV &H0154 ### *####################################### *-------------------------------------------------------------------------------- * (XX) SHIFT SUBCMD AND HBYTE AND LBYTE TO CO-PROCESSOR AND RECEIVE HBYTE AND LBYTE FROM CO-PROCESSOR *-------------------------------------------------------------------------------- 0154 9B XX: SEI ;set INTE bit, disabling interrupts (NO INTERRUPTS) 0155 AD 54 BSR SRQ ;REQUEST AND ACKNOWLEDGE * on SRQ return: CLOCK is input, DATA is output *------- SET LINES TO OUTPUT ------------- 0157 AD 38 BSR SETDOUT ;set PORT1 (DATA, PB0) and PORT2 (CLOCK, PB1) as output *------- SOME DELAY ------ 0159 AE 0C LDX #12 ;store 12 in x-register (DELAY AND CLR X) 015B 5A ADEL: DEC X ;decrement x-register 015C 26 FD BNE ADEL ;jump to increment *------ SEND SUBCOMMAND ------- 015E B6 A3 LDA SUBCMD ;put SUBCMD into accu 0160 CD 01 F7 JSR SOAKKU ;clock/shift accu-value into coprocessor *----- SEND COMMAND HI-BYTE --- 0163 B6 A2 LDA BUFFH ;put HBYTE into accu 0165 CD 01 7F JSR SOAKKU ;clock/shift accu-value into coprocessor *----- SEND COMMAND LO-BYTE --- 0168 B6 A1 LDA BUFFL ;put LBYTE into accu 016A CD 01 7F JSR SOAKKU ;clock/shift accu-value into coprocessor *----- SET LINES TO IN ------- 016D 11 05 BCLR 0,PADDR ;set PB0/Port1 as input (DATA LINE IN) 016F 13 05 BCLR 1,PADDR ;set PB1/Port2 as input (CLOCK LINE IN) *---receive-hbyte-and-lbyte-from-co-processor--- 0171 CD 01 98 JSR SIAKKU ;gosub SIAKKU, load byte received from co-processor into accu [GET HI-BYTE] 0174 B7 A2 STA BUFFH ;store accu in HBYTE 0176 CD 01 98 JSR SIAKKU ;gosub SIAKKU, load byte received from co-processor into accu [GET LO-BYTE] 0179 B7 A1 STA BUFFL ;store accu in LBYTE *----- SET LINES TO OUT 017B AD 14 BSR SETDOUT ;gosub SETDOUT, set PORT1 (DATA, PB0) and PORT2 (CLOCK, PB1) as output 017D 9A CLI ;enable all interrupts 017E 81 RTS ;return ********************************************************************************* * * :---0---:---1---:---2---:---3---:---4---:---5---:---6---:---7---: * * -----------+ +-----+ +-----+ +-----+ +-----+ +-----+ +----- * DATA-----------+ | 1 | | 1 | | 1 | | 1 | 0 0 | 1 | | 1 example byte * -----------+-+ +-+ +-+ +-+ +-------+-------+-+ +-+ * +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ * CLOCK--+ |1| |2| |3| |4| |5| |6| |7| |8| * +-----------+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +- * ********************************************************************************* *-------------------------------------------------------------------------------- (SOAKKU) SHIFT OUT ACCU (TO CO-PROCESSOR) *-------------------------------------------------------------------------------- 017F 5F SOAKKU: CLRX ;clear x-register 0180 13 01 S1BYT: BCLR 1,PADAT ;set PB1 low (CLOCK OUT L) 0182 44 LSRA ;shift accu to left (b0 FIRST) (into carry) 0183 11 01 BCLR 0,PADAT ;set PB0 low (DATA OUT LO) 0185 24 02 BCC CLKOUT ;if bit carry is clear, jump 0187 10 01 BSET 0,PADAT ;set PB0 hig (DATA OUT HI) 0189 12 01 CLKOUT: BSET 1,PADAT ;set PB1 hig, CLOCK OUT H 018B 5C INC X ;increment x-register 018C A3 08 CPX #$8 ;check for x-register equals 8 018E 26 F0 BNE S1BYT ;if not, jump 0190 81 RTS ;if yes, return * - sets PB0/PB1 as output *------------------------------ *--- SET DATA OUT ------- *------------------------------ ; ; ; ; ; ; ; *SETDOUT: BSET 1,PADDR ;SET CLOCKLINE OUT 0191 13 01 SETDOUT:BCLR 1,PADAT ;set CLOCK low I12.14, PA1, [CLOCK LO] 0193 12 05 BSET 1,PADDR ;switch CLOCK to output, I12.14, PA1, [SET CLOCKLINE OUT] 0195 10 05 BSET 0,PADDR ;switch DATA to output, I12.15, PA0, [SET DATALINE OUT] 0197 81 RTS ;return *-------------------------------------------------------------------------------- * (SHIFT IN AKKU) STORE SERIAL RECEIVED DATA FROM PORT1 (CLOCKED IN BY 'CLOCK') INTO ACCUMULATOR *-------------------------------------------------------------------------------- 0198 5F SIAKKU: CLRX ;clr X-register 0199 02 01 FD R1BYT: BRSET 1,PADAT,R1BYT ;loop here until PORT2 (CLOCK) is low [WAIT CLOCK L] 019C 44 LSRA ;shift accu left 1 bit (sets or clears carry) 019D 03 01 FD CLKIN: BRCLR 1,PADAT,CLKIN ;loop here until PORT2 (CLOCK) is high [WAIT CLOCK H] 01A0 01 01 02 BRCLR 0,PADAT,SDT ;if PORT1 (DATA) is low, then jump to SDT 01A3 AA 80 ORA #$80 ;if DATA is high, set bit 7 in accu 01A5 5C SDT: INC X ;increment X-register 01A6 A3 08 CPX #$08 ;check if X-register equals 8 (all 8 DATA bits received) 01A8 26 EF BNE R1BYT ;if X-register not equals 8, then jump back to R1BYT 01AA 81 RTS ;return *-------------------------------------------------------------------------------- * (SRQ) SERVICE REQUEST, CALL CO-PROCESSOR AND WAIT UNTIL CO-PROCESSOR IS READY TO RECEIVE DATA * * on exit: CLOCK is input, DATA is output *-------------------------------------------------------------------------------- ********************************************************************************* * -------+---------------------------------------- * DATA ???????+ * -------+---------------------------------------- * * ---+ +---//---+ +---wait-for-low---//---+ * CLOCK ???+?+ | +---+iiiiiiiiiiiiiiiiiiiiiii| * ---+-+---+-+ +------------------//---+----- * //=36us //=100us(guess) * |-----------------endless-repeat-------------| * ********************************************************************************* * Conrad uses (confusing) name 'PADAT' (Port A DATa) for microcontroller 8-bits Port B(!) * Conrad PORT1 = microprocessor port B bit 0 (PB0, pin 39), used as DATA signal to/from Co-processor IC I2 (PA0, pin 15) * Conrad PORT2 = microprocessor port B bit 1 (PB1, pin 38), used as CLOCK signal to/from Co-processor IC I2 (PA1, pin 14) * - Microcontroller bits PORT1 and PORT2 are directly connected to the co-processor. * - PORT1 is used as DATA signal TO the co-processor. main-processor is sending, co-processor is receiving * - PORT2 is used as CLOCK signal TO the co-processor. main-processor is sending, co-processor is receiving * - PORT1 is used as DATA signal FROM the co-processor. main-processor is receiving, co-processor is sending * - PORT2 is used as CLOCK signal FROM the co-processor. main-processor is receiving, co-processor is sending * ********************************************************************************* 01AB AD E4 SRQ: BSR SETDOUT ;gosub SETDOUT (switch PORT1 and PORT2 as output [LINES TO OUT]) 01AD 12 01 BSET 1,PADAT ;set PORT2 high. (CLOCK = 1) (why?) *---delay-of-36us-(36-micro-seconds)--- 01AF AE 0A LDX #10 ;put value 10 in x-register 01B1 5A DEL1: DEX ;decrement x-reg, [HOLD REQUEST 36 us] 01B2 26 FD BNE DEL1 ;if x-register is nonzero, then jump back to DEL1 *------ WAIT FOR ACKNOWLEDGE --- 01B4 13 05 BCLR 1,PADDR ;switch PORT2 (CLOCK) to input [END REQUEST] 01B6 AE 0A LDX #10 ;store 10 in x-register 01B8 02 01 05 DEL2: BRSET 1,PADAT,ACKN ;if PORT1 (CLOCK) is high (by co-processor), then goto ACKN 01BB 5A DEX ;decrement x-register [WAIT ACKN] 01BC 26 FA BNE DEL2 ;if x-register is not 0, goto DEL2 01BE 20 EB BRA SRQ ;goto SRQ [REPEAT AFTER TIMEOUT] *----- ACKNOWLEDGE RECEIVED ---- 01C0 02 01 FD ACKN: BRSET 1,PADAT,ACKN ;if CLOCK is high, goto ACKN (current line repeating), if low, goto next line 01C3 81 RTS ;return *####################################### *### define PLM_SLOW &H01C4 ### *####################################### * ********************************************************************************* * * Warnig from b6r4.pdf microcontroller documentation * * Warning: Because the SFA bit and SFB bit are not double buffered, it is mandatory to set the SFA * bit and SFB bit to the desired values before writing to the PLMA/PLMB registers; not doing so * could temporary give incorrect values at the PLM outputs. * ********************************************************************************* 01C4 A6 0C LDA #$0C ;set FSA bit and FSC bit for MISC reggister 01C6 B7 0C STA MISC ;store settings into MISC register 01C8 81 RTS ;return *####################################### *### define SYSTEM &H01C9 ### *####################################### * *--+ +---+ +---+ +---+ +---+ +---+ * | | 1 | | 1 | | 1 | 0 0 | 1 | | 1 | 0 PB0, Serial-Data (sdio) * +-+ +-+ +-+ +-----+-----+-+ +-+ +-----+------- * +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ * |1| |2| |3| |4| |5| |6| |7| |8| PB2, Serial Clock (sclio) *-----+ +---+ +---+ +---+ +---+ +---+ +---+ +---+ +-------- * +-+ * | | PB3, Strobe (strobe) *-----------------------------------------------------+ +-- * *-------------------------------------------------------------------------------- * PDRIVE: (0x01C9) COPY DATA FROM EXTPORT REGISTER INTO SHIFTEGISTER CHIP IC I11 *-------------------------------------------------------------------------------- * REMAINS PA3=0, PA2=1 ;Conrad comment ; ; ; ; ; ; ; ; ; ; 01C9 AE 08 PDRIVE: LDX #8 ;load 0x08 in X-register 01cB 39 A4 LP2: ROL EXTP ;rotate left EXTPORT (carry is set or clr, according outshifted bit) 01CD 11 01 BCLR 0,PADAT ;clr port B bit 0 (PORT1, IC I11.2) Serial-Data=0 (LO OUT) 01CF 24 02 BCC LP1 ;if no carry, branch to LP1 01D1 10 01 BSET 0,PADAT ;set port B bit 0 (PORT1, IC I11.2) Serial-Data=1 (HI OUT) *---negative-pulse-on-clock---(inverted by harware to positive puls) 01D3 15 01 LP1: BCLR 2,PADAT ;clr port B bit 2 (PORT3, IC I11.3) Serial-Clck=1 (inverted) s(CLOCK) 01D5 14 01 BSET 2,PADAT ;set port B bit 2 (PORT3, IC I11.3, Serial-Clck=0 (inverted) s(CLOCK) *---count-bits-done--- 01D7 5A DEX ;decrement X-register (8->7->6->5->4->3->2->1->0) 01D8 26 F1 BNE LP2 ;if X-register is not zero, then jump back to LP2 *---rotate-one-extra-to-make-bit0-in-carry-go-into-bit0-position--- 01DA 39 A4 ROL EXTP ;rotate left EXTPORT (carry is set or clr, according outshifted bit) *---generate-a-positive-pulse-on-strobe--- 01DC 16 01 BSET 3,PADAT ;set port B bit 3 (PORT4, IC I11.1) Strobe=1 [STROBE] 01DE 17 01 BCLR 3,PADAT ;clr port B bit 3 (PORT4, IC I11.1, Strobe=0 [STROBE] *---return--- 01E0 81 RTS ;return *####################################### *### define ACS_LO &H01E1 ### *####################################### *-------------------------------------------------------------------------------- * ACSLO: (0x01E1) SET ACS INFRARED TRANSMIT SIGNAL TO LOW POWER *-------------------------------------------------------------------------------- 01E1 AD 12 ACSLO: BSR CLRF ;call subroutine CRLF (clear all ACS bits) 01E3 14 A4 BSET 2,EXTP ;set bit 2 in EXTPORT (ACS_PWR_HI) 01E5 1C A5 BSET 6,SYSSTAT ;clr bit 6 in SYSTEM_STATUS (ACS_PWR_HI) 01E7 20 E0 BRA PDRIVE ;goto PDRIVE *####################################### *### define ACS_HI &H01E9 ### *####################################### *-------------------------------------------------------------------------------- * ACSHI: (0x01E9) SET ACS INFRARED TRANSMIT SIGNAL TO HIGH POWER *-------------------------------------------------------------------------------- 01E9 AD 0A ACSHI: BSR CLRF ;call subroutine CRLF (clear all ACS bits) 01EB 12 A4 BSET 1,EXTP ;set bit 1 in EXTPORT (ACS_PWR_LO) 01ED 1A A5 BSET 5,SYSSTAT ;set bit 6 in SYSTEM_STATUS (ACS_PWR_HI) 01EF 20 D8 BRA PDRIVE ;goto PDRIVE *####################################### *### define ACS_MAX &H01F1 ### *####################################### *-------------------------------------------------------------------------------- * ACSMAX: (0x01F1) SET ACS INFRARED TRANSMIT SIGNAL TO MAXIMUM POWER *-------------------------------------------------------------------------------- 01F1 AD 02 ACSMAX: BSR CLRF ;call subroutine CRLF (clear all ACS bits) 01F3 20 D4 BRA PDRIVE ;goto PDRIVE *-------------------------------------------------------------------------------- * CRLF: (0x01F5) CLEAR ACS BITS IN EXTPORT REGISTER AND IN SYSTEM_STATUS REGISTER *-------------------------------------------------------------------------------- 01F5 15 A4 CLRF: BCLR 2,EXTP ;clr bit 2 in EXTPORT (ACS_PWR_HI) 01F7 13 A4 BCLR 1,EXTP ;clr bit 1 in EXTPORT (ACS_PWR_LO) 01F9 1D A5 BCLR 6,SYSSTAT ;clr bit 6 in SYSTEM_STATUS (ACS_PWR_HI) 01FB 1B A5 BCLR 5,SYSSTAT ;clr bit 5 in SYSTEM_STATUS (ACS_PWR_LO) 01FD 81 RTS ;return